La nanoelectrònica cerca el substitut de l'òxid de silici

La comunitat científica internacional investiga les possibilitats de substitució de l'òxid de silici, un dels components principals dels dispositius microelectrònics, per altres materials amb millors propietats elèctriques i compatibles amb els processos de fabricació CMOS (Semiconductor Complementari d'Oxid de Metall). El Departament d'Enginyeria Electrònica de la UAB, juntament amb el centre europeu d'investigació IMEC, ha estudiat alguns d'aquests elements utilitzant tècniques amb resolució espacial nanomètrica.La comunidad científica internacional investiga las posibilidades de sustitución del óxido de silicio, uno de los componentes principales de los dispositivos microelectrónicos, por otros materiales con mejores propiedades eléctricas y compatibles con los procesos de fabricación CMOS (Semiconductor Complementario de Oxido de Metal). El Departamento de Ingeniería Electrònica de la UAB, junto con el centro europeo de investigación IMEC, ha estudiado algunos de estos elementos utilizando técnicas con resolución espacial nanométrica

Caracterització a escala nanomètrica de la degradació i ruptura dielèctrica del SiO2 en dispositius MOS mitjançant C-AFM

Consultable des del TDXTítol obtingut de la portada digitalitzadaLa progressiva reducció del gruix de l'òxid de porta (SiO2) en dispositius MOS sense el corresponent escalat en tensions, ha donat lloc a l'aparició de mecanismes de fallada (ruptura forta, HBD; ruptura suau, SBD; ruptura progressiva, PBD; o corrents de fuites, SILC) que en limiten la seva fiabilitat. Alguns d'aquests mecanismes, menys severs que la ruptura forta (SBD, PBD i SILC), han plantejat nous interrogants a l'hora d'establir la relació que hi ha entre la ruptura (BD) de l'òxid i la fallada del dispositiu o circuit del qual forma part. Per aquest motiu, a fi de determinar el grau de sensibilitat dels circuits a la ruptura dielèctrica, cal estudiar amb més profunditat els factors que en controlen la seva severitat. En aquest sentit, els tests estàndards de caracterització elèctrica no representen de manera gaire acurada les condicions reals d'estrés dels dispositius MOS. Treballs recents, en canvi, indiquen que l'estrés limitat en corrent (CLS), sí permet simular millor les condicions reals d'operació. Actualment és àmpliament acceptat que la ruptura de l'òxid és (i) un fenomen extremadament local que es desencadena en àrees de l'ordre de 10-13-10-12cm2 i (ii) la conseqüència d'un procés de degradació en el qual l'estructura de l'òxid es modifica progressivament i que s'ha associat a la generació de trampes durant l'estrés elèctric. El caràcter extremadament local d'aquests fenòmens fa que sigui necessària una anàlisi a la mateixa escala on tenen lloc: a escala nanomètrica. Amb aquesta finalitat, en aquesta tesi s'ha analitzat la fenomenologia de pre- i post-ruptura en capes primes de SiO2 (2.9-5.9nm) amb C-AFM (Conductive Atomic Force Microscope). L'elevada resolució lateral d'aquesta tècnica (~10nm) ha permès caracteritzar la degradació i la ruptura dielèctrica (així com l'efecte del límit de corrent) d'òxids de porta a escala nanomètrica. Durant l'etapa de degradació, s'han observat canvis sobtats i transitoris en la conductivitat de l'òxid, atribuïts a l'atrapament/ desatrapament de càrregues elementals en els defectes generats durant l'estrés elèctric. Aquesta fenomenologia s'ha relacionat amb el soroll de pre-ruptura observat en dispositius de grandària microelectrònica. El soroll de pre-ruptura s'ha registrat en estressos a tensió constant (CVS) en forma de RTS (Random Telegraph Signal). Una anàlisi temporal i freqüencial demostra que els resultats obtinguts són compatibles amb els corresponents a estructures amb elèctrode de porta. A més, amb C-AFM s'ha pogut mesurar d'una manera directa la característica I-V d'un spot de pre-ruptura i s'ha trobat que té un comportament similar a l'observat en memòries flash amb corrents de fuites anòmals. En aquesta tesi també s'ha analitzat la ruptura de l'òxid, fent especial èmfasi en els efectes del límit de corrent en l'esdeveniment BD. Òxids de porta sense elèctrode metàl·lic s'han estressat amb la punta del microscopi amb i sense límit de corrent fins a desencadenar la ruptura. Després de l'esdeveniment BD, s'han registrat corrents més elevats en la zona afectada i, en alguns casos, també s'han observat canvis en les imatges topogràfiques. Aquests canvis morfològics s'han relacionat amb la càrrega elèctrica negativa present a l'òxid després de la ruptura (BINC), que s'ha associat amb el mal estructural induït durant l'esdeveniment BD. La quantitat de BINC s'ha estimat a partir de les alçades de les protuberàncies observades en les imatges topogràfiques obtingudes amb C-AFM i s'ha trobat que és superior en el cas d'estressos sense límit de corrent. A partir de les imatges de corrent també s'ha trobat que la ruptura, tot i desencadenar-se en àrees molt petites (de l'ordre de ~100nm2), es propaga lateralment a àrees veïnes SBD. El valor de SBD es veu fortament afectat per la severitat de la ruptura dielèctrica que, al mateix temps, depèn del corrent que flueix a través de l'òxid en el moment en el qual es desencadena l'esdeveniment BD. Quan s'apliquen CLS, SBD està limitada a un àrea de ~3.1 104nm2 mentre que, quan no hi ha límit de corrent, les àrees afectades són superiors (~1.6 105nm2). Aquests resultats doncs, demostren que el límit de corrent no permet el desenvolupament complet del canal percolatiu, deixant l'òxid en un estat metaestable que es perllonga fins que les condicions elèctriques d'estrés canvien. Finalment, també s'ha demostrat que amb C-AFM és possible localitzar i analitzar spots de ruptura induïts en dispositius microelectrònics (amb elèctrode de porta) mitjançant les tècniques de caracterització estàndard. Tots aquests resultats demostren la capacitat del C-AFM d'analitzar en detall l'efecte del límit de corrent en la ruptura dielèctrica, així com l'impacte de la ruptura en la funcionalitat del dispositiu microelectrònic.The progressive decrease of the gate oxide (SiO2) thickness in MOS devices without the corresponding bias voltages scaling, has provoked the appearance of failure mechanisms (hard breakdown, HBD; soft breakdown, SBD; progressive breakdown, PBD; and the stress induced leakage current, SILC) that limit the oxide reliability. Some of these mechanisms (SBD, PBD and SILC) are not as hard as the HBD event, and that has questioned the relation between the oxide breakdown (BD) and the device or circuit failure. For this reason, to determine the actual sensitivity of circuits to oxide breakdown, it is necessary to study the factors that control the severity of the BD event. In this direction, the standard electrical tests are not representative of the actual stress conditions of MOS devices. Recent works, however, point out the current limited stress (CLS) as a better testing methodology to simulate the actual operation conditions. Nowadays it is accepted that the oxide failure is (i) an extremely local phenomenon that takes place in areas of the order of 10-12-10-13cm2 and (ii) the consequence of a degradation stage during which the oxide structure is progressively modified, and that has been associated to the generation of defects during the electrical stress. The extremely local nature of both phenomenon makes necessary an analysis at the same scale where they take place: at a nanometer scale. With this purpose, in this thesis the pre- and post-BD phenomenology has been analysed in thin SiO2 films (2.9-5.9nm) with C-AFM (Conductive Atomic Force Microscope). The high lateral resolution of this technique (~10nm) allows the electrical characterization of the degradation and breakdown event (as well as the effect of the current limitation) of gate oxides at a nanometer scale. During the degradation stage, sudden changes of the oxide conductivity have been observed, attributed to the trapping/detrapping of elementary charges in/from the defects generated during the electrical stress. This phenomenology has been related to the pre-BD noise observed in microelectronic devices. This pre-BD noise is measured during a Constant Voltage Stress (CVS) in form of Random Telegraph Signal (RTS). A time and frequency analysis show compatible parameters to those obtained in poly-gated structure. Moreover, the C-AFM has allowed the direct measurement of the I-V curve of a fluctuating spot, which has been found to be similar to those reported for the anomalous leakage current in flash memory devices. The BD of the oxide has been also analysed in this thesis, paying an special attention to the effects of a current limitation during the BD transient. Bare oxides have been stressed until BD using the tip of the microscope as the metal electrode, with and without setting a current limit. After BD, larger currents are measured at the BD location (as expected) and, sometimes, some changes are also observed in the topography images. These morphological changes have been related to the negative charge present in the oxide after the oxide BD (BINC), which has been associated to the structural damage induced by the BD event. The amount of BINC has been quantified from the heights of the hillocks observed in the C-AFM topography images and has been found to be larger in the case of non-limited current stresses. From the current images, it has been shown that, although the BD takes place in a very small area (So, few hundreds of nm2) it is laterally propagated to a larger area, SBD. The value of SBD is strongly affected by the BD hardness which, at the same time, depends on the current that flows at the location where BD is triggered. When CLS are applied, the growth of SBD is limited to an area of ~3.1 104nm2 whereas, when there is no current limit, larger areas are affected ( ~1.6 105nm2). The results also show that the current limit does not allow the complete development of the BD path, leaving the oxide in a metastable configuration that lasts until the electrical environment is changed. Finally, it has also been demonstrated that with C-AFM it is possible to locate and characterize BD spots induced in microelectronic devices (poly-gated) with standard electrical tests. The results show that C-AFM is a powerful tool to analyze in detail the effect of current limitation on the breakdown event and, conversely, the impact of BD on the device and circuit performance

Oxide Breakdown Spot Spatial Patterns as Fingerprints for Optical Physical Unclonable Functions

Dielectric Breakdown (BD) of the gate oxide in a Metal-Insulator-Semiconductor (MIS) or Metal-Insulator-Metal (MIM) structure has been traditionally considered a major drawback since such event can seriously affect the electrical performance of the circuit containing the device. However, since BD is an inherently random process, when externally detectable by optical means, the phenomenon can be used to generate cryptographic keys for Physically Unclonable Functions (PUFs). This is the case discussed here. Images containing BD spot spatial distributions in MIM devices were binarized and their uniformity, uniqueness and reproducibility evaluated as fingerprints for security applications such as anti-counterfeiting purposes, secure identification and authentication of components. The obtained results are highly promising since it is demonstrated that the generated fingerprints meet all the mandatory requirements for PUFs, indicating that the proposed approach is potentially useful for this kind of applications

Nanometer-scale electrical characterization of stressed ultrathin SiO2 films using conducting atomic force microscopy

A conductive atomic force microscope has been used to electrically stress and to investigate the effects of degradation in the conduction properties of ultrathin (<6 nm) SiO2 films on a nanometer scale (areas of ≈100 nm2). Before oxide breakdown, switching between two states of well-defined conductivity and sudden changes of conductivity were observed, which are attributed to the capture/release of single charges in the defects generated during stress

Breakdown-induced negative charge in ultrathin SiO2 films measured by atomic force microscopy

Atomic-force-microscopy-based techniques have been used to investigate at a nanometer scale the dielectric breakdown (BD) of ultrathin (<6 nm) SiO2films of metal-oxide-semiconductordevices. The results show that BD leads to negative charge at the BD location and the amount of created charge has been estimated. Moreover, the comparison of the charge magnitude generated during current-limited stresses and stresses without current limit demonstrates that the observed BD induced negative charge is related to the structural damage created by the oxide BD

Monitoring defects in III-V materials : a nanoscale CAFM study

The implementation of high mobility devices requires growing III-V materials on silicon substrates. However, due to the lattice mismatch between these materials, III-V semiconductors tend to develop structural defects affecting device electrical characteristics. In this study, the CAFM technique is employed for identification and analysis of nanoscale defects, in particular, Threading Dislocations (TD), Stacking faults (SF) and Anti-phase Boundaries (APB), in III-V materials grown over silicon wafers

Correlation between the nanoscale electrical and morphological properties of crystallized hafnium oxide-based metal oxide semiconductor structures

The relationship between electrical and structuralcharacteristics of polycrystalline HfO2films has been investigated by conductive atomic force microscopy under ultrahigh vacuum conditions. The results demonstrate that highly conductive and breakdown (BD) sites are concentrated mainly at the grain boundaries (GBs). Higher conductivity at the GBs is found to be related to their intrinsic electrical properties, while the positions of the electrical stress-induced BD sites correlate to the local thinning of the dielectric. The results indicate that variations in the local characteristics of the high-k film caused by its crystallization may have a strong impact on the electrical characteristics of high-k dielectric stacks

Polycrystallization effects on the nanoscale electrical properties of high-k dielectrics

In this study, atomic force microscopy-related techniques have been used to investigate, at the nanoscale, how the polycrystallization of an Al₂O₃-based gate stack, after a thermal annealing process, affects the variability of its electrical properties. The impact of an electrical stress on the electrical conduction and the charge trapping of amorphous and polycrystalline Al₂O₃ layers have been also analyzed

Channel-Hot-Carrier degradation of strained MOSFETs : A device level and nanoscale combined approach

Strained MOSFETs with SiGe at the source/drain regions and different channel lengths have been studied at the nanoscale with a conductive atomic force microscope (CAFM) and at device level, before and after channel-hot-carrier (CHC) stress. The results show that although strained devices have a larger mobility, they are more sensitive to CHC stress. This effect has been observed to be larger in short channel devices. The higher susceptibility of strained MOSFETs to the stress has been related to a larger density of defects close to the diffusions, as suggested by CAFM data